2006 Mahatma Gandhi University M.Sc Electronic Science VLSI Design and Analysis Question paper for exam preparation. Question paper for 2006 Mahatma Gandhi University M.Sc Electronic Science VLSI Design and Analysis Question paper, Exam Question papers 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2012 university in india question papers. SiteMap
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2006 Mahatma Gandhi University M.Sc Electronic Science VLSI Design and Analysis Question paper

University Question Papers
2006 Mahatma Gandhi University M.Sc Electronic Science VLSI Design and Analysis Question paper
M.Sc. DEGREE EXAMINATION, AUGUST 2006

Second Semester

Branch : Electronics

Mech. 203 T – VLSI DESIGN AND ANALYSIS

Time : Three Hours Maximum : 75 Marks

Part A

Answer any six questions.
Each question carries 2 marks.

1. Write an expression for the threshold voltage of MOS transistor. Explain the symbols used.
2. Sketch the current versus input voltage curve for CMOS inverter.
3. What is meant by native transistor?
4. Explain a model for dynamic register.
5. Distinguish between Moore and Mealy machines.
6. Sketch the twin tub structure.
7. Define sheet resistance.
8. What are the advantages of CMOS process over bipolar?
9. Explain body effect.
(6 X 2 = 12 marks)

Part B

Answer any three questions.
Each question carries 5 marks.

10. What is latch up problem in CMOS? How is it remedied?
11. Sketch a scheme to implement OR gate using transmission gates.
12. Sketch the circuit of CMOS based half adder and corresponding stick diagram.
13. Draw the block diagram of OM system and explain its different sections.
14. What is the significance of ?-based design rules? Explain the rules for wires.
(3 X 5 = 15 marks)

Part C

Answer all questions.
Each question carries 12 marks.

15. (a) Discuss the effects of scaling in CMOS process.
Or
(b) Describe the p-well and n-well processes. Compare them.
16. (a) Explain the structure of PLA. How is it implemented with CMOS?
Or
(b) Explain the implementation of CMOS based D flip-flop.
17. (a) Explain the diffusion process. What are the various parameters involved in this?
Or
(b) Discuss the functions and limitations of interconnects in chip design.
18. (a) Sketch the V-I curve for MOSFET. Explain the different regions of operation and the parameters involved.
Or
(b) With suitable models, analyze the different types of delays introduced by the CMOS inverter.
(4 X 12 = 48 marks)



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