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2005 M C A Computer System Architecture Question paper

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2005 M C A Computer System Architecture Question paper
End-Term Examination
Second Semester [MCA] – MAY 2005

Paper Code: MCA-106 Subject: Computer System Architecture

Time: 3 Hours Maximum Marks: 60

Note: Q. 1 is co mpulsory. Other questions have two alternative to choose from.

Q. 1 Justify or refute the following statement clearly, citing examples whether
(a) A combinational shifter is less efficient as compared with a sequential shifter, as it
requires extra multiplexers. 3
(b) Indirect addressing usually reduces the amount of assembly code for a given
program, as compared to direct addressing. 3
(c) Since the “Interrupt Enable” (IEN) is disabled automatically during an interrupt
cycle if a pending interrupt is deleted, therefore no further interrupt can be served
while executing the ISR. 3
(d) Since associative caches are addressed by content, there is no need for separate
address lines to access individual locations of the caches, as in RAM. 3
(e) The burst mode of DMA transfer is more efficient for data transfers to / from
magnetic disks but rather inefficient for data tr ansfer to / from magnetic tap es.
(f) Code written in RTL helps us to design digital systems systematically. 3
(g) An array multiplier’s speed is bottlenecked b y the same time taken to add the
partial operand together. 2


Q. 2 Alternate 1:-
(a) An atomic (or indivisible) memory operation comprises a memory read, modify
and a memor y write operations in an unbroken sequence. Show the micro
operations in an unbroken sequence. Show the micro operations to carr y out this
read modify write cycle. Also, draw a schematic showing the hardware
components to carry out this memory operation. 6

(b) Briefly describe the various categories of instructions in a general purpose
microprocessor. Suppose that you have to design the instruction set architecture
for a special purpose microprocessor that carries o ut basic graphic functions, what
extra instruction(s) and register(s) would you suggest? 4


Alternate 2:-
(a) A microprocessor checks its INTR line during the last clock cycle of each
instruction cycle, and sets a flag R if there is a pending interrupt. In the first clock
cycle of the current instruction, if R is high, the processor output INTA and
checks bits b2, b3, b4 of its data bus. If then stores a 32 bit return address in a
byte addressable memory at a location which is 8x (b4b3b2) and jumps to the next
location. Illustrate the sequence of events durin g the interrupt cycle with a flow
chart. 5

(b) Briefly outline the working o f a two pass assembler, indicating the core steps and
outputs generated during each pass. 5


Q. 3 Alternate 1:-
(a) Describe the typical format of a vertically encoded microinstruction. Write the
“Fetch” routine and the “execute” routine for the LOAD microinstruction.
Assume a microprocessor with an accumulator, other basic registers and 2-
operand format. You may use symbolic forms of the micro-operations needed. 6
(b) What are the typical applications and the limitation of (i) Relative addressing
mode (ii) Based, indexed addressing mode. 4

Alternate -2 :-
(a) “Today; traditionally C ISC microprocessors employ RISC characteristics,
whereas RISC microprocessor emplo y CISC characteristics”. Explain this
comment with illustrative examples. 5

(b) A program contains 1000 machine instructions. These are executed in a 7 stage
instruction pipeline. Due to various data dependencies, 10 cycles are wasted for
every batch of 50 instructions. Branch instructions cause a fu rther wastage of 20%
extra cycles. Calculate the speed up of the pipeline as compared to a non-pipeline
processor. 5


Q. 4 Alternate 1 :-
(a) A microprocessor multiplexes data from four different data terminals, and sends
the multiplexed data over a telephone link to a remote unit, via a UART. Suggest
the most suitable I/O communication scheme (such as parallel, serial,
synchronous, asynchronous, strobed, handshaked) between :
(i) The data terminals and the microprocessor
(ii) The microprocessor and the UART.
(iii) The UART and the remote unit 5

(b) Using Booths algorithm, illustrate the sequence of steps in a tabular fashion, when
11101 is multiplied with 10111. 5

Alternate 2 :-

(a) A 512-bits data packet needs to be prepared with 16-bit words, for serial
asynchronous communication. There is 1 start bit and 1.5 stop bits for each word.
The data packet is then encapsulated with an 8-bit SOH, 8 bit ETX and 16 bit
CRC. Calculate the total overhead (in percentage) of transferrin g 1000 such
packets. 5

(b) Draw a flow chart showing the steps of floating point addition. Illustrate the
sequence of steps with the binary equivalents of 0.34375 and 0.125, stored in their
normalized forms. 5


Q. 5 Alternate 1:-
(a) Compare the direct mapped cache system with the associatively mapped cached
system in terms of design, flex ibility, cost, replacement technique and impact on
hit ratio. 5

(b) A magnetic disk has the following characteristics: 5
- Seek time to reach 0th (outermost) track = 8 ms and seek time to reach
300th (inner most) track =14 ms. Assume a linearly increasing seek time
within this interval.
- Rotational speed = 3600 rpm
- Number of bits per track = 4096
- No. of bits per sector = 512

Calculate the time taken to read a 32 K bits file that starts on the 3rd sector of the
200th track.
Assume the average rotational latency to locate the first sector. i.e. start of file.

Alternate 2 :-

(a) Enumerate some requirements which are needed specially fo r multiprocessor
system from the viewpoint of memory processor failures, communication and
software. 6

(b) A computer system needs 2 KB of RAM, 2KB of ROM and 3 I/O ports with 3
registers in each. The first 1 KB of memory space is occupied by ROM and
finally the I/O port addresses. To construct this memory system 512 x 8 RAM
chips are used. Show the complete memory map of the system. 4

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